Silicon neuromorphic systems have a large, distributed array of computation units (called neurons) that operate with extremely sparse, data-dependent activity at relatively slow timescales. Communicating events between these computation units with direct, point-to-point wiring is difficult for a large-scale system. The standard approach to this problem is to leverage the speed of modern CMOS and use time-multiplexed wires for communication. Address-event representation (AER) is an example of such event-driven encoding and communication protocol which was originally proposed to communicate the location and timing information of sparse neural events between neuromorphic chips. A variety of schemes have been proposed in the literature for designing an AER-based communication interface based on the event or activity pattern.
We designed two new encoding schemes which offer a significant improvement in latency, throughput, and power compared to existing approaches.
For situations where the event (activity) pattern is unknown, HTR handles event with the help of a hierarchical ring structure.
When the event (activity) pattern is known, FP-AER configures into a topology that works best for the given activity pattern.